Phase-Locked Loop Basics, PLL

A phase-locked loop (PLL) is a closed-loop frequency-control system based on the phase difference between the input clock signal and the feedback clock signal of a controlled oscillator. Figure 1 shows a simplified block diagram of the major components in a PLL. The main blocks of the PLL are the phase frequency detector (PFD), charge pump, loop filter, voltage controlled oscillator (VCO), and counters, such as a feedback counter (M), a pre-scale counter (N), and post-scale counters(C).

Figure 1. PLL Block Diagram

PLL: Phase-locked loop PLL Block Diagram

PLLs in Altera® FPGAs align the rising edge of the reference input clock to a feedback clock using the PFD. The falling edges are determined by the duty-cycle specified by the user. The PFD detects the difference in phase and frequency between the reference clock and feedback clock inputs and generates an “up” or “down” control signal based on whether the feedback frequency is lagging or leading the reference frequency. These “up” or “down” control signals determine whether the VCO needs to operate at a higher or lower frequency, respectively.

The PFD outputs these “up” and “down” signals to a charge pump. If the charge pump receives an up signal, current is driven into the loop filter. Conversely, if it receives a down signal, current is drawn from the loop filter.

The loop filter converts these signals to a control voltage that is used to bias the VCO. Based on the control voltage, the VCO oscillates at a higher or lower frequency, which affects the phase and frequency of the feedback clock. If the PFD produces an up signal, then the VCO frequency increases. A down signal decreases the VCO frequency. The VCO stabilizes once the reference clock and the feedback clock have the same phase and frequency. The loop filter filters out jitter by removing glitches from the charge pump and preventing voltage over-shoot.

When the reference clock and the feedback clock are aligned, the PLL is considered locked. To find reasons why a PLL may lose lock, see Why Does My PLL Lose Lock?

A divide counter (M) is inserted in the feedback loop to increase the VCO frequency above the input reference frequency. VCO frequency (FVCO) is equal to (M) times the input reference clock (FREF). The PFD input reference clock (FREF) is equal to the input clock (FIN) divided by the pre-scale counter (N). Therefore, the feedback clock (FFB) applied to one input of the PFD is locked to the FREF that is applied to the other input of the PFD. The VCO output feeds post-scale counters which allow a number of harmonically related frequencies to be produced within the PLL.

The output frequency of the PLL is equal to the VCO frequency (FVCO) divided by the post-scale counter (C).

In the form of equations:

FREF = FIN / N
FVCO = FREF × M = FIN × M/N
FOUT = FVCO / C = (FREF × M) / C = (FIN × M) / (N × C)

where:

FVCO = VCO frequency
FIN = input frequency
FREF = reference frequency
FOUT = output frequency
M = counter (multiplier), part of the clock feedback path
N = counter (divider), part of the input clock reference path
C = post-scale counter (divider)