Selasa, 29 November 2011
PEMBANGKIT GELOMBANG FM
STANDING WAVE RATIO
Standing wave ratio disingkat SWR kadang-kadang disingkat dengan nama VSWR (Voltage Standing Wave Ratio). Bila impedansi saluran transmisi tidak sesuai dengan transceiver maka akan timbul daya refleksi (reflected power) pada saluran yang berinterferensi dengan daya maju (forward power). Interferensi ini
CARA MENGHITUNG PANJANG KABEL ANTENA
panjang kabel
(300/frek) x velocity coax x kelipatan ganjil
contoh
frek di 100 Mhz pake kabel rg 58 kabel yang tersedia 14 meter
(300/100) x 0.66 x 5 = 9.9 bila terlalu panjang motongnya
(300/100) x 0.66 x 7 = 13.86...paling mendekati 14 meter
(300/frek) x velocity coax x kelipatan ganjil
contoh
frek di 100 Mhz pake kabel rg 58 kabel yang tersedia 14 meter
(300/100) x 0.66 x 5 = 9.9 bila terlalu panjang motongnya
(300/100) x 0.66 x 7 = 13.86...paling mendekati 14 meter
Contoh penggunaan tabel velocity.
CARA MENGHITUNG ANTENA
1 lamda = 300/F
ya udah .. kalo 5/8 - 6/8 - 3/4 - 1/4 Hitungan dibawah mempergunakan yg 5/8 Lamda
300/f x5 / 8
contoh f 100 MHz =
300/100 = 3meter x 5 = 15 meter / 8 = 1,875 meter
jadi 5/8 pada frek 100MHz = 1,875 Meter
di jadikan cm = 1,875 meter = 187,500 centimeter
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hitungan ini biasanya meleset sedikit sekian cm
---> logam alumunium = 0.95
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ya udah .. kalo 5/8 - 6/8 - 3/4 - 1/4 Hitungan dibawah mempergunakan yg 5/8 Lamda
300/f x5 / 8
contoh f 100 MHz =
300/100 = 3meter x 5 = 15 meter / 8 = 1,875 meter
jadi 5/8 pada frek 100MHz = 1,875 Meter
di jadikan cm = 1,875 meter = 187,500 centimeter
To view links or images in this forum your post count must be 1 or greater. You currently have 0 posts.
hitungan ini biasanya meleset sedikit sekian cm
---> logam alumunium = 0.95
To view links or images in this forum your post count must be 1 or greater. You currently have 0 posts.
Ngemacth Kabel
ada tip and trik gak ya untuk memilih coax kabel yang bagus, (sejenis RG8), kemudian gimana cara mach line coax pada suatu frekuensi misal 143.550Mhz, bisa dihitung gak ya mach impedansinya dari panjang kabelnya yang digunakan, soalnya ada teman yang mach antena pake potong-potong kabel, sampe habis -+ 5meter, dari panjang sebelumnya
Minggu, 27 November 2011
BEM F.TEKNIK DATANGI SMA PGRI 2 SUBANG
Dalam rangka untuk meningkatkan kuantitas mahasiswa di fakultas teknik Universitas Subang, Badan Eksekutif Mahasiswa (BEM) Fakultas Teknik mulai menjalankan program "Goes To School part I". Program yang telah di agendakan oleh BEM ini di awali dengan mendatangi SMA PGRI 2 Subang pada hari Sabtu,26 November 2011.
Sabtu, 26 November 2011
Rabu, 23 November 2011
Senin, 21 November 2011
Phase-Locked Loop Basics, PLL
A phase-locked loop (PLL) is a closed-loop frequency-control system based on the phase difference between the input clock signal and the feedback clock signal of a controlled oscillator. Figure 1 shows a simplified block diagram of the major components in a PLL. The main blocks of the PLL are the phase frequency detector (PFD), charge pump, loop filter, voltage controlled oscillator (VCO), and counters, such as a feedback counter (M), a pre-scale counter (N), and post-scale counters(C).
Figure 1. PLL Block Diagram
PLL: Phase-locked loop PLL Block Diagram
PLLs in Altera® FPGAs align the rising edge of the reference input clock to a feedback clock using the PFD. The falling edges are determined by the duty-cycle specified by the user. The PFD detects the difference in phase and frequency between the reference clock and feedback clock inputs and generates an “up” or “down” control signal based on whether the feedback frequency is lagging or leading the reference frequency. These “up” or “down” control signals determine whether the VCO needs to operate at a higher or lower frequency, respectively.
The PFD outputs these “up” and “down” signals to a charge pump. If the charge pump receives an up signal, current is driven into the loop filter. Conversely, if it receives a down signal, current is drawn from the loop filter.
The loop filter converts these signals to a control voltage that is used to bias the VCO. Based on the control voltage, the VCO oscillates at a higher or lower frequency, which affects the phase and frequency of the feedback clock. If the PFD produces an up signal, then the VCO frequency increases. A down signal decreases the VCO frequency. The VCO stabilizes once the reference clock and the feedback clock have the same phase and frequency. The loop filter filters out jitter by removing glitches from the charge pump and preventing voltage over-shoot.
When the reference clock and the feedback clock are aligned, the PLL is considered locked. To find reasons why a PLL may lose lock, see Why Does My PLL Lose Lock?
A divide counter (M) is inserted in the feedback loop to increase the VCO frequency above the input reference frequency. VCO frequency (FVCO) is equal to (M) times the input reference clock (FREF). The PFD input reference clock (FREF) is equal to the input clock (FIN) divided by the pre-scale counter (N). Therefore, the feedback clock (FFB) applied to one input of the PFD is locked to the FREF that is applied to the other input of the PFD. The VCO output feeds post-scale counters which allow a number of harmonically related frequencies to be produced within the PLL.
The output frequency of the PLL is equal to the VCO frequency (FVCO) divided by the post-scale counter (C).
In the form of equations:
FREF = FIN / N
FVCO = FREF × M = FIN × M/N
FOUT = FVCO / C = (FREF × M) / C = (FIN × M) / (N × C)
where:
FVCO = VCO frequency
FIN = input frequency
FREF = reference frequency
FOUT = output frequency
M = counter (multiplier), part of the clock feedback path
N = counter (divider), part of the input clock reference path
C = post-scale counter (divider)
Figure 1. PLL Block Diagram
PLL: Phase-locked loop PLL Block Diagram
PLLs in Altera® FPGAs align the rising edge of the reference input clock to a feedback clock using the PFD. The falling edges are determined by the duty-cycle specified by the user. The PFD detects the difference in phase and frequency between the reference clock and feedback clock inputs and generates an “up” or “down” control signal based on whether the feedback frequency is lagging or leading the reference frequency. These “up” or “down” control signals determine whether the VCO needs to operate at a higher or lower frequency, respectively.
The PFD outputs these “up” and “down” signals to a charge pump. If the charge pump receives an up signal, current is driven into the loop filter. Conversely, if it receives a down signal, current is drawn from the loop filter.
The loop filter converts these signals to a control voltage that is used to bias the VCO. Based on the control voltage, the VCO oscillates at a higher or lower frequency, which affects the phase and frequency of the feedback clock. If the PFD produces an up signal, then the VCO frequency increases. A down signal decreases the VCO frequency. The VCO stabilizes once the reference clock and the feedback clock have the same phase and frequency. The loop filter filters out jitter by removing glitches from the charge pump and preventing voltage over-shoot.
When the reference clock and the feedback clock are aligned, the PLL is considered locked. To find reasons why a PLL may lose lock, see Why Does My PLL Lose Lock?
A divide counter (M) is inserted in the feedback loop to increase the VCO frequency above the input reference frequency. VCO frequency (FVCO) is equal to (M) times the input reference clock (FREF). The PFD input reference clock (FREF) is equal to the input clock (FIN) divided by the pre-scale counter (N). Therefore, the feedback clock (FFB) applied to one input of the PFD is locked to the FREF that is applied to the other input of the PFD. The VCO output feeds post-scale counters which allow a number of harmonically related frequencies to be produced within the PLL.
The output frequency of the PLL is equal to the VCO frequency (FVCO) divided by the post-scale counter (C).
In the form of equations:
FREF = FIN / N
FVCO = FREF × M = FIN × M/N
FOUT = FVCO / C = (FREF × M) / C = (FIN × M) / (N × C)
where:
FVCO = VCO frequency
FIN = input frequency
FREF = reference frequency
FOUT = output frequency
M = counter (multiplier), part of the clock feedback path
N = counter (divider), part of the input clock reference path
C = post-scale counter (divider)
Jumat, 11 November 2011
PROPOSAL RADIO ELSIMA MENJADI UKM (UNIT KEGIATAN MAHASISWA)
A. LATAR BELAKANG
Sumber daya manusia sebagai modal dasar maju dan berkembangnya suatu bangsa dan negara perlu adanya peningkatan dan penempaan, Terutama yang terkait dengan kesadaran masyarakat akan pentingnya pendidikan. Hal ini dilakukan mengingat semakin terbuka luasnya wawasan dan cakrawala dunia dalam era globalisasi khususnya dalam bidang pendidikan. Penyebaran informasi yang bermanfaat dan arus juga dibutuhkan oleh masyarakat. Agar pendidikan dan budaya bangsa yang dimiliki dapat terjaga integritasnya, atau dengan melakukan upaya menjalin persaudaraan, persatuan, kesatuan, antar bangsa umumnya, dan organisasi/komunitas/ kelompok / seniman – seniman dan masyarakat pecinta seni khususnya di Kabupaten Subang.
Media radio siaran merupakan salah satu media massa elektronik yang terbukti efektif dalam meningkatkan penyampaian arus informasi dan komunikasi di masyarakat, khususnya masyarakat di Kabupaten Subang.
Sebagai mahasisiwa, yang biasa di katakanan agent of change perlu adanya wadah kegitan yang bersifat independent dan terarah. Dalam memotifasi hal tersebuat maka perlu adanya media yang dapat menyalurkan hobby dan minat serta sebagai pengamalan dari Tridharma Perguruan tinggi. Sebab mahasiswa dituntut untuk kreatif, inovatif serta produktif dalam menghadapi zaman.
Salah satu bentuk partisipasi kongkrit kami dalam rangka membuka wawasan dan cakrawala dunia dalam penyampaian informasi yang bermanfaat, aktual, transparan dan dapat dipertanggungjawabkan, serta untuk lebih mengupayakan pemanfaatan sumber daya manusia, apresiasi seni, dan pengembangan minat dan bakat mahasiswa maka ELSIMA yang berada di frekuensi 107.8 FM berkedudukan dan beralamat di Jalan Arief Rachman Hakim No.08 Subang Jawa Barat bermaksud menjadi Unit Kegiatan Mahasiswa (UKM) yang
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